Link: https://eu02web.zoom-x.de/j/66719911736?pwd=N5n96kFJbauLi2u79eJI0ZD15hgNsi.1
4:30pm Central European time is (usually) 7:30am Pacific time and 11:30pm Beijing time
Energy efficiency is the most important challenge in AI computing. Orders of magnitude improvements in energy efficiency are required to enable new AI capabilities and deploy existing features that are too power-intensive to allow large-scale use. Although they are extremely energy efficient, current digital CMOS-based architectures, including graphics processing units (GPUs) and tensor processing units (TPUs), are no longer significantly improving energy efficiency with technology node scaling and appear to have reached a limit of ~5 tera operations per second per watt (TOPs/W). This has led to rising interest in alternative architectures such as analog in-memory computing (AIMC), where neural network weights are stored as analog conductance states of nonvolatile memories and matrix math is performed using fundamental circuit laws. Although AIMC is predicted to be capable of >100 TOPS/W – enough to profoundly impact AI computing – it has yet to be commercially realized. This is due to challenging device-level requirements that must be met to ensure application-level accuracy on par with existing digital systems. These requirements include low conductance variability, noise, drift, and conductance magnitude, as well as long retention and tolerance of environmental variations, such as temperature changes and radiation. Our work is focused on advancing two promising device candidates to meet the goals of AIMC: TaOx-based resistive memory (ReRAM) and Cu-based electrochemical memory (ECRAM). ReRAM is already integrated with CMOS in advanced foundry nodes, but use as an analog weight is complicated by the intrinsic variability, noise, drift, and temperature dependence of this filamentary switching device. However, recent work has demonstrated the possibility of mitigating these effects through the combined optimization of materials and fabrication processes, advanced write-verify routines, and device-aware circuits and algorithms. Cu-ECRAM is a novel, three-terminal ionic device that is not yet available in foundries, but which exhibits nearly ideal properties for AIMC due to the bulk conduction mechanism. Promising electrical characteristics, including negligible variability, noise, and drift, low conductance (in the nS range), and long retention, have been demonstrated. Furthermore, our dual ion ECRAM combines protons and Cu ions to implement “fast” (protons) and “slow” (Cu) electrical behavior, which may be useful in future AI systems. This talk will discuss the recent progress on these resistive devices and compare them with mature nonvolatile memories such as flash.
Matthew Marinella is Associate Professor in the School of Electrical, Computer and Energy Engineering at ASU, where he leads a research group dedicated to advancing electronic and ionic memory technologies for energy efficient and resilient AI computing. He is PI of a major Microelectronics Commons effort to create the robust, analog, radiation-hardened resistive memory technology required by spaceborne in-sensor AI computing.
From 2010 to 2021, he was with Sandia’s Microsystems S&T Center, where he was most recently Distinguished Member of the Technical Staff. At Sandia, Dr. Marinella led numerous substantial projects that created new CMOS+X technologies and architectures for energy-efficient and extreme-environment computing. As the Learning Hardware Task Lead for the Hardware Acceleration of Adaptive Neural Algorithms (HAANA) Project, Dr. Marinella led a team that pioneered the use of emerging electrochemical and oxide-based ionic memory devices for neural network training and created multiscale modeling frameworks to understand and improve the accuracy of analog in-memory computing accelerators. He also served as Lead Scientist for Sandia’s Beyond Moore Computing Lab and DOE-level initiatives, contributing to U.S. microelectronics policy and growing Sandia’s footprint in emerging technologies.
Prof. Marinella has published extensively in the area of emerging memory devices for energy efficient, analog in-memory, neuromorphic, and radiation-hardened computing (over 8,000 citations, h-index=41), given numerous invited and contributed talks, and presented several short courses on these topics. He has served in technical advising and leadership roles in various Lab- and DOE-level initiatives on next generation computing for government applications and is a member of the SRC Decadal Plan Executive Committee, a member of the Microelectronics and Advanced Packaging Technologies (MAPT) Roadmap, and chairs the Emerging Memory Devices Section for the IRDS Roadmap Beyond CMOS Chapter. Dr. Marinella is a member of the Board of Review Editors for Science, serves on the technical program committees of several conferences, and is a Senior Member of the IEEE.
Prior to starting at Sandia in 2010, he was a Device Engineer in Microchip’s Technology Development Group. He received his PhD in Electrical Engineering from Arizona State University under Dieter K. Schroder in 2008.
